Ignore empty parameters in Verilog module instantiations
authorClaire Xenia Wolf <claire@symbioticeda.com>
Thu, 1 Oct 2020 16:26:53 +0000 (18:26 +0200)
committerClaire Xenia Wolf <claire@symbioticeda.com>
Thu, 1 Oct 2020 16:27:16 +0000 (18:27 +0200)
commit46f0932c4c61aca3ab5332f99a4a60d110b52191
treec33b214a81a2967dd550b93339ba1b9cf0596a07
parent7e2fc2eaeb70179c8da3e5dc8be800f486d5b912
Ignore empty parameters in Verilog module instantiations

Fixes #2394

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
frontends/verilog/verilog_parser.y