git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Wesley W. Terpstra <wesley@sifive.com>
	Wed, 22 Mar 2017 20:57:56 +0000 (13:57 -0700)
committer	Wesley W. Terpstra <wesley@sifive.com>
	Wed, 22 Mar 2017 21:21:54 +0000 (14:21 -0700)
commit	46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb
tree	1ff563929c13be279340ad439af8692d3c9913aa	tree
parent	693fc45eb8ccc3c9f84b898de3119a172e0776f5	commit \| diff

riscv: replace rtc device with a real clint implementation

Simple-V augmented version of spike