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(parent: 3371563) | patch
Added SAT generator and simple sat_solve command
authorClifford Wolf <clifford@clifford.at>
Fri, 7 Jun 2013 11:59:13 +0000 (13:59 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 7 Jun 2013 11:59:13 +0000 (13:59 +0200)
commit46fbe9d26299a7b6197463b3056d778f525658fb
tree748b515d870f60b047e77e4b3e93257a116ccb46tree
parent3371563f2f14ce0d6bc7798d0fc802b54aae93c8commit | diff
Added SAT generator and simple sat_solve command
frontends/verilog/const2ast.cc diff | blob | history
frontends/verilog/parser.y diff | blob | history
kernel/satgen.h [new file with mode: 0644] blob
passes/sat/Makefile.inc [new file with mode: 0644] blob
passes/sat/example.v [new file with mode: 0644] blob
passes/sat/example.ys [new file with mode: 0644] blob
passes/sat/sat_solve.cc [new file with mode: 0644] blob