Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
authorClifford Wolf <clifford@clifford.at>
Sat, 16 Aug 2014 16:18:30 +0000 (18:18 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 16 Aug 2014 16:29:39 +0000 (18:29 +0200)
commit47c2637a961839f1eb1a0386f7e54d94be50bc10
tree2db3bfbabf1ad7ca21176c2639b565720655fb8b
parent56a30cf42c6a40f265a67df6e2c5fa74657fbf5b
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
backends/verilog/verilog_backend.cc
kernel/celltypes.h
kernel/consteval.h
kernel/rtlil.cc
kernel/satgen.h
manual/CHAPTER_CellLib.tex
passes/abc/abc.cc
techlibs/common/simcells.v