Added read_verilog -sv options, added support for bit, logic,
authorClifford Wolf <clifford@clifford.at>
Thu, 12 Jun 2014 09:54:20 +0000 (11:54 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 12 Jun 2014 09:54:20 +0000 (11:54 +0200)
commit482d9208aa9dacb7afe21f08c882d4881581013a
treea5a4d409f7d84cc2dc6283dcf45df3aea02cb061
parent9a6cd64fc2ca46c9aed1bd03b6898c7734420c53
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
README
frontends/verilog/lexer.l
frontends/verilog/parser.y
frontends/verilog/verilog_frontend.cc
frontends/verilog/verilog_frontend.h
tests/sat/asserts.ys
tests/sat/asserts_seq.ys