Add simulated UART design
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 27 Aug 2019 14:08:54 +0000 (00:08 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Mon, 9 Sep 2019 12:18:48 +0000 (22:18 +1000)
commit48b689b665c8620e3477b183f5c5db98625b9018
tree32fa29a574a056ed4ee05dfd2dc8a5fb2e6d2fa2
parent2241b716749938a7b4743fac0035f5ca359ffda0
Add simulated UART design

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
sim_uart.vhdl [new file with mode: 0644]