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(parent: b6345b1) | patch
Read bigger Verilog files.
authorKaj Tuomi <kaj.tuomi@siru.fi>
Sat, 18 May 2019 11:20:30 +0000 (14:20 +0300)
committerKaj Tuomi <kaj.tuomi@siru.fi>
Sat, 18 May 2019 11:20:30 +0000 (14:20 +0300)
commit48ddbe52fb1428fc8f7f3d6444c5637eb151475f
tree64bdc5903bf099d59aa9ba9dacff03d8b7a9eda2tree
parentb6345b111d994ff0de1bcd91379db1c289feb03bcommit | diff
Read bigger Verilog files.

Hit parser limit with 3M gate design. This commit fix it.
frontends/verilog/Makefile.inc diff | blob | history