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(parent: 9789d25) | patch
Multiply needs to be 16 stages to fix all timing issues
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 26 Sep 2019 00:53:55 +0000 (10:53 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 30 Sep 2019 03:54:32 +0000 (13:54 +1000)
commit48e6e719d302b0484c608a51788a02fca0c2ce43
tree04ee3b96ded7b035a594ce4223709a5ebb1b6d3atree
parent9789d258fb1f0edbf0cc7e45eac1b2e7625633cbcommit | diff
Multiply needs to be 16 stages to fix all timing issues

This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
multiply.vhdl diff | blob | history