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(parent: cce6b86) | patch
hdl.ast: prohibit shifts by signed value.
authorwhitequark <whitequark@whitequark.org>
Sat, 1 Feb 2020 23:04:25 +0000 (23:04 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 1 Feb 2020 23:04:25 +0000 (23:04 +0000)
commit49758a3a0c4866fc09c84b011e52f9bf692ea570
tree141dd1a8be203d613c118fcc9d0db65303ab43batree
parentcce6b8687bd03f11d65cdd13730a3ac5e9eb34efcommit | diff
hdl.ast: prohibit shifts by signed value.

These are not desirable in a HDL, and currently elaborate to broken
RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like
we already do for division and modulo.

Fixes #302.
nmigen/back/pysim.py diff | blob | history
nmigen/hdl/ast.py diff | blob | history
nmigen/test/test_hdl_ast.py diff | blob | history
nmigen/test/test_sim.py diff | blob | history