[AArch64] Fix wrong-code bug in right-shift SISD patterns
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Fri, 20 Feb 2015 14:05:51 +0000 (14:05 +0000)
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>
Fri, 20 Feb 2015 14:05:51 +0000 (14:05 +0000)
commit498b13e24b8a995dd3bb6f0bb734f15b78ef89d1
tree4cf8cd26b5ea9500187020a5b5fad34f124e8436
parent739b41ebb1350735fe3aa92c1978524204395df8
[AArch64] Fix wrong-code bug in right-shift SISD patterns

* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_<mode>3):
Mark operand 0 as earlyclobber in 2nd alternative.
(1st define_split below *aarch64_lshr_sisd_or_int_<mode>3):
Write negated shift amount into QI lowpart operand 0 and use it
in the shift step.
(2nd define_split below *aarch64_lshr_sisd_or_int_<mode>3): Likewise.

* gcc.target/aarch64/sisd-shft-neg_1.c: New test.

From-SVN: r220860
gcc/ChangeLog
gcc/config/aarch64/aarch64.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c [new file with mode: 0644]