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(parent: f1fba99) | patch
intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal
authorJordan Justen <jordan.l.justen@intel.com>
Tue, 16 Apr 2019 07:42:45 +0000 (00:42 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Mon, 22 Jun 2020 18:41:59 +0000 (11:41 -0700)
commit49fe43e15fdfc5be4523638776cb2a96f92e04f0
treec1b6b52a8be290e679daee3508b2cbee0873fd8ctree
parentf1fba99695f4dc036b17bee02d99a62efdbe21f7commit | diff
intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal

An example entry with URB size being 0 is in the cnl list.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
src/intel/common/gen_l3_config.c diff | blob | history