RISC-V: Add T-Head Fmv vendor extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Sun, 13 Nov 2022 15:59:20 +0000 (16:59 +0100)
committerNelson Chu <nelson@rivosinc.com>
Thu, 17 Nov 2022 08:43:49 +0000 (16:43 +0800)
commit4a3bc79bf4c0e89c876c930a1e95a02213277460
tree4a82c5fbaf454ec2fcf147c1134d67b2f38d5879
parent7a4ce4a1bcff9710b7dede9797e6d5eb2364c06e
RISC-V: Add T-Head Fmv vendor extension

This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/elfxx-riscv.c
gas/NEWS
gas/doc/c-riscv.texi
gas/testsuite/gas/riscv/x-thead-fmv.d [new file with mode: 0644]
gas/testsuite/gas/riscv/x-thead-fmv.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-opc.c