git.libre-soc.org Git - gem5.git/commit

projects / gem5.git / commit

summary | shortlog | log | commit | commitdiff | tree
(parent: 035a82e) | patch

author	Curtis Dunham <Curtis.Dunham@arm.com>
	Tue, 29 Apr 2014 21:05:02 +0000 (16:05 -0500)
committer	Curtis Dunham <Curtis.Dunham@arm.com>
	Tue, 29 Apr 2014 21:05:02 +0000 (16:05 -0500)
commit	4a3f11149d791284a012af71067f6b2199aa165c
tree	c960b2f2c5e23fc37e238f423a8bbc3b73419213	tree
parent	035a82ee2c7e9ee72163a6559f721b242427906d	commit \| diff

arm: use condition code registers for ARM ISA

Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.

15 files changed:

src/arch/arm/ccregs.hh	[new file with mode: 0644]	blob
src/arch/arm/faults.cc		diff \| blob \| history
src/arch/arm/insts/static_inst.cc		diff \| blob \| history
src/arch/arm/intregs.hh		diff \| blob \| history
src/arch/arm/isa.cc		diff \| blob \| history
src/arch/arm/isa.hh		diff \| blob \| history
src/arch/arm/isa/operands.isa		diff \| blob \| history
src/arch/arm/miscregs.hh		diff \| blob \| history
src/arch/arm/nativetrace.cc		diff \| blob \| history
src/arch/arm/registers.hh		diff \| blob \| history
src/arch/arm/utility.cc		diff \| blob \| history
src/cpu/o3/O3CPU.py		diff \| blob \| history
src/cpu/simple_thread.hh		diff \| blob \| history
src/sim/serialize.hh		diff \| blob \| history
util/cpt_upgrader.py		diff \| blob \| history