mem: Make MemCtrl a ClockedObject
authorWendy Elsasser <wendy.elsasser@arm.com>
Sat, 8 Feb 2020 00:00:57 +0000 (18:00 -0600)
committerJason Lowe-Power <power.jg@gmail.com>
Tue, 8 Sep 2020 16:38:47 +0000 (16:38 +0000)
commit4acc419b6fa5ea7bbc1cf128e75be1cc263557b0
treed2c5255d1bc18db4e210294f6eaabb8fc0443aab
parent518e79ad2df51c6abe0af15259c5477ec0c1425c
mem: Make MemCtrl a ClockedObject

Made DRAMCtrl a ClockedObject, with DRAMInterface
defined as an AbstractMemory. The address
ranges are now defined per interface. Currently
the model only includes a DRAMInterface but this
can be expanded for other media types.

The controller object includes a parameter to the
interface, which is setup when gem5 is configured.

Change-Id: I6a368b845d574a713c7196c5671188ca8c1dc5e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28968
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
26 files changed:
configs/common/MemConfig.py
configs/dram/low_power_sweep.py
configs/dram/sweep.py
configs/example/memcheck.py
configs/learning_gem5/part1/simple.py
configs/learning_gem5/part1/two_level.py
configs/learning_gem5/part2/simple_cache.py
configs/learning_gem5/part2/simple_memobj.py
configs/learning_gem5/part3/simple_ruby.py
configs/ruby/Ruby.py
src/mem/DRAMCtrl.py
src/mem/DRAMInterface.py [new file with mode: 0644]
src/mem/SConscript
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh
src/mem/drampower.cc
src/mem/drampower.hh
src/mem/qos/QoSMemCtrl.py
src/mem/qos/QoSMemSinkCtrl.py
src/mem/qos/QoSMemSinkInterface.py [new file with mode: 0644]
src/mem/qos/SConscript
src/mem/qos/mem_ctrl.cc
src/mem/qos/mem_ctrl.hh
src/mem/qos/mem_sink.cc
src/mem/qos/mem_sink.hh
tests/gem5/configs/base_config.py