[arm]: redefine aes patterns

[arm]: redefine aes patterns

This patch removes the arch-common aese/aesmc and aesd/aesimc fusions
(i.e. aes fusion) implemented in the scheduling phase through the
aarch_crypto_can_dual function. The reason is due to observing
undesired behaviour in cases such as:
- when register allocation goes bad (e.g. extra movs)
- aes operations with xor and zeroed keys among interleaved operations

A more stable version should be provided by instead doing the aes fusion
during the combine pass. As such, new combine patterns have been added to
enable this.

The second change is the aese and aesd patterns have been rewritten as
encapsulating a xor operation. The purpose is to simplify the need of
having additional combine patterns for cases like the ones below:

For AESE (though it also applies to AESD as both have a xor operation):

    data = data ^ key;
    data = vaeseq_u8(data, zero);
    ---
    veor        q1, q0, q1
    aese.8      q1, q9

Should mean and generate the same as:

    data = vaeseq_u8(data, key);
    ---
    aese.8       q1, q0

2019-07-09  Sylvia Taylor  <sylvia.taylor@arm.com>

	* config/arm/crypto.md:
	(crypto_<crypto_pattern>): Redefine aese/aesd pattern with xor.
	(crypto_<crypto_pattern>): Remove attribute enabled for aesmc.
	(crypto_<crypto_pattern>): Split CRYPTO_BINARY into 2 patterns.
	(*aarch32_crypto_aese_fused, *aarch32_crypto_aesd_fused): New.
	* config/arm/arm.c
	(aarch_macro_fusion_pair_p): Remove aes/aesmc fusion check.
	* config/arm/aarch-common-protos.h
	(aarch_crypto_can_dual_issue): Remove.
	* config/arm/aarch-common.c
	(aarch_crypto_can_dual_issue): Likewise.
	* config/arm/exynos-m1.md: Remove aese/aesmc fusion.
	* config/arm/cortex-a53.md: Likewise.
	* config/arm/cortex-a57.md: Likewise.
	* config/arm/iterators.md:
	(CRYPTO_BINARY): Redefine.
	(CRYPTO_UNARY): Removed.
	(CRYPTO_AES, CRYPTO_AESMC): New.

	* gcc.target/arm/aes-fuse-1.c: New.
	* gcc.target/arm/aes-fuse-2.c: New.
	* gcc.target/arm/aes_xor_combine.c: New.

From-SVN: r273296