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(parent: 6c76890) | patch
Fix DAR/DSISR reading before they are written
authorMichael Neuling <mikey@neuling.org>
Mon, 8 Feb 2021 09:17:48 +0000 (20:17 +1100)
committerMichael Neuling <mikey@neuling.org>
Mon, 8 Feb 2021 09:20:27 +0000 (20:20 +1100)
commit4c21587c4d0dcd6fdacf742fdd5454823919831e
tree616e585bc648f0f69aedc0df1195daa9855708c5tree
parent6c7689052dbd76b5fe7c9f4804d6a4817e9845afcommit | diff
Fix DAR/DSISR reading before they are written

If the DAR and DSISR are read before they are written, we assert with:

  register_file.vhdl:55:25:@60195ns:(report note): Writing GPR 09 00000000XXXXXXXX
  register_file.vhdl:61:17:@60195ns:(assertion failure): Assertion violation

This initialises DAR/DSISR to avoid this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
loadstore1.vhdl diff | blob | history