i965: Update GS state for Broadwell.
authorKenneth Graunke <kenneth@whitecape.org>
Tue, 5 Nov 2013 07:19:55 +0000 (23:19 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Sat, 1 Feb 2014 01:50:08 +0000 (17:50 -0800)
commit4c4e0ed64bceca57e19c0a9f53aae77d795aa937
tree50c6927258e4983f99ee5457ad4d4b27c79a2dc7
parenta0d4311072267aa5427eb2cacd820e96f114eba0
i965: Update GS state for Broadwell.

This is quite similar to the Gen7 code.  The main changes:
 - 48-bit relocations
 - Thread count is specified as U/2-1 instead of U-1.
 - An extra DWord (DW9) with clip planes, URB entry output length/offsets
 - We need to program the "Expected Vertex Count" (VerticesIn)

v2: Set the number of binding table entries so they can be prefetched
    (requested by Eric Anholt).
v3: Add a WARN_ONCE for a missing workaround.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
src/mesa/drivers/dri/i965/Makefile.sources
src/mesa/drivers/dri/i965/brw_defines.h
src/mesa/drivers/dri/i965/brw_state.h
src/mesa/drivers/dri/i965/brw_state_upload.c
src/mesa/drivers/dri/i965/gen8_gs_state.c [new file with mode: 0644]