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anv: Improve brw_nir_lower_mem_access_bit_sizes
authorJason Ekstrand <jason@jlekstrand.net>
Fri, 27 Mar 2020 01:10:40 +0000 (20:10 -0500)
committerMarge Bot <eric+marge@anholt.net>
Fri, 3 Apr 2020 20:26:54 +0000 (20:26 +0000)
commit4c8b1003889bfb0f708d91dc7caa08a37f9caef4
tree41cedc5c2fd84f337ae995c6b5dfcc0b86fdd566tree
parentc6439792287f11f25cb2b62d699f52daefe54a44commit | diff
anv: Improve brw_nir_lower_mem_access_bit_sizes

This commit makes us take both bit size and alignment into account so
that we can properly handle cases such as when we have a 32-bit store
to an 8-bit-aligned address.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c diff | blob | history