FDCE ports to be alphabetical
authorEddie Hung <eddie@fpgeh.com>
Tue, 31 Dec 2019 23:24:02 +0000 (15:24 -0800)
committerEddie Hung <eddie@fpgeh.com>
Tue, 31 Dec 2019 23:24:02 +0000 (15:24 -0800)
commit4cdba00e25d892b90c0ee48716c17dec60e472db
tree6f85162ff0715af2cf03c7d835119a95c0d6d8c0
parentb4663a987bc1bac3aa4cccab99dc191825902205
FDCE ports to be alphabetical
techlibs/xilinx/cells_sim.v