Add simple VHDL+PSL example
authorClifford Wolf <clifford@clifford.at>
Fri, 28 Jul 2017 13:33:30 +0000 (15:33 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 28 Jul 2017 15:39:43 +0000 (17:39 +0200)
commit4cf890dac121dc977fc4507168b48e47aecf5c46
tree35f53140121d1d2eb6e0412f994b31d8562b2a43
parent5a828fff34ae8e0da7d887232daa516db1e37a21
Add simple VHDL+PSL example
tests/sva/.gitignore
tests/sva/Makefile
tests/sva/runtest.sh
tests/sva/vhdlpsl00.vhd [new file with mode: 0644]