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(parent: 9f8f0eb) | patch
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 1 May 2019 10:58:44 +0000 (12:58 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 1 May 2019 10:59:04 +0000 (12:59 +0200)
commit4dccb8a9eb305d52d30e9c2e563d1b814a6585a5
tree309cbc5c18b31392da87971e41ad54f2623b0e5ctree
parent9f8f0eb18e6543a4d5ce6beef97e1014273e603ecommit | diff
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
litex/soc/interconnect/axi.py diff | blob | history