back.verilog: detect undriven public wires using Yosys.
authorwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 04:51:15 +0000 (04:51 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 04:59:48 +0000 (04:59 +0000)
commit4e32f6b8de2ea4ae37e1c698c1b17a3fe90ff234
treeff2c9ee2243e66893e31fe2c57e5ad720c412012
parent27d3dfc45374d6e157ef4fa7ee5821fa9011e77c
back.verilog: detect undriven public wires using Yosys.

This should never happen, and is certainly a logic bug in nMigen.
nmigen/back/verilog.py