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(parent: 01fed67) | patch
radeonsi: align all CE dumps to L2 cache line size
authorMarek Olšák <marek.olsak@amd.com>
Tue, 1 Aug 2017 12:26:21 +0000 (14:26 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 7 Aug 2017 19:12:24 +0000 (21:12 +0200)
commit4e629ca7c768c62c530887ff61e96fba2cce6717
tree6e237991a5f6c6d95ba6339586a148b4855eef6ctree
parent01fed6760886a266d99922fb6562644fe0c74868commit | diff
radeonsi: align all CE dumps to L2 cache line size

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeonsi/si_descriptors.c diff | blob | history