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(parent: e59b7cc) | patch
split step counter into clock and substep
authorJacob Lifshay <programmerjake@gmail.com>
Fri, 6 May 2022 03:10:32 +0000 (20:10 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Fri, 6 May 2022 03:10:32 +0000 (20:10 -0700)
commit4ee201e6cae8475621647f7b3b9839292ed0b46f
tree500a8a651ca7aed1cadb3445661e539b5e618d01tree
parente59b7ccf6c066fc0ecac6410e9b6447d5af77533commit | diff
split step counter into clock and substep

this allows substep to be completely optimized away by yosys for CLDivRemFSMStage
src/nmigen_gf/hdl/cldivrem.py diff | blob | history
src/nmigen_gf/hdl/test/test_cldivrem.py diff | blob | history