verilog: allow spaces in macro arguments
authorZachary Snow <zach@zachjs.com>
Wed, 20 Jan 2021 15:49:32 +0000 (08:49 -0700)
committerZachary Snow <zach@zachjs.com>
Wed, 20 Jan 2021 15:49:58 +0000 (08:49 -0700)
commit4fadcc8f25d5ef1e494aa7d5e49d893afdaa1705
treea9a800ae8beb09260763e122371f009eda689b23
parent4762cc06c6b7cd36dda2e6eddf15b9782334ccd4
verilog: allow spaces in macro arguments
frontends/verilog/preproc.cc
tests/simple/macro_arg_spaces.sv [new file with mode: 0644]