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(parent: e727a0e) | patch
arm: invalidate TLB miscreg cache on modification of HSCTLR
authorDylan Johnson <Dylan.Johnson@ARM.com>
Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)
committerDylan Johnson <Dylan.Johnson@ARM.com>
Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)
commit4fbf40daab480ae02b75a75e0dd5f56ce38386d2
treeda3988cf1979f5b7b655661ede690cc0b23aa01dtree
parente727a0eeaa5f2d46921c8496d77623a9704d40b6commit | diff
arm: invalidate TLB miscreg cache on modification of HSCTLR

Change-Id: I5212c91c56435fe008950ed99feacc6921609226
src/arch/arm/isa.cc diff | blob | history