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(parent: 4474687) | patch
cores: add External Memory Interface (EMIF) Wishbone bridge.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 12 Apr 2020 14:34:33 +0000 (16:34 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 12 Apr 2020 14:34:33 +0000 (16:34 +0200)
commit4fe31f0760ca98994d4b8c9b867cfff686412c7d
tree407d9d57c07fde65e5000ca0f2ac5c29c305a2a7tree
parent44746870a730048bc757ec3f9ba1ed2a513eb7afcommit | diff
cores: add External Memory Interface (EMIF) Wishbone bridge.

Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
litex/soc/cores/emif.py [new file with mode: 0644] blob
test/test_emif.py [new file with mode: 0644] blob