aarch64: Add support for predicate-as-counter registers

aarch64: Add support for predicate-as-counter registers

SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks.  In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.

This patch adds support for these registers and extends some
existing instructions to support them.  Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.