Two fixes to try and get TLB miss cost more in line with real platform:
authorSteve Reinhardt <stever@eecs.umich.edu>
Wed, 2 Mar 2005 03:32:14 +0000 (22:32 -0500)
committerSteve Reinhardt <stever@eecs.umich.edu>
Wed, 2 Mar 2005 03:32:14 +0000 (22:32 -0500)
commit50a4ed87d0dc548e55d607381d0aecc35b02caf6
tree3df3b888e3a4746d5930e199c4026ad17c286855
parentd9de7c57837fa24177b8604daad638100c4e013a
Two fixes to try and get TLB miss cost more in line with real platform:
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
arch/alpha/isa_desc