git.libre-soc.org Git - yosys.git/commit

author	Larry Doolittle <ldoolitt@recycle.lbl.gov>
	Thu, 5 Oct 2017 00:01:30 +0000 (17:01 -0700)
committer	Clifford Wolf <clifford@clifford.at>
	Thu, 5 Oct 2017 14:23:49 +0000 (16:23 +0200)
commit	50bcd9a728ff89f220873b3345c4e18a65c4a37f
tree	ff7b306d49b46ec25b7bfac26ca9ace82302a3f0	tree
parent	fc3378916dbaf46018a99571ef190189088c225c	commit \| diff

Clean whitespace and permissions in techlibs/intel

21 files changed:

techlibs/intel/Makefile.inc	[changed mode: 0755->0644]	blob \| history
techlibs/intel/a10gx/cells_arith.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/a10gx/cells_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/a10gx/cells_sim.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/common/altpll_bb.v		diff \| blob \| history
techlibs/intel/common/brams.txt	[changed mode: 0755->0644]	blob \| history
techlibs/intel/common/brams_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/common/m9k_bb.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneiv/cells_arith.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneiv/cells_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneiv/cells_sim.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneive/arith_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneive/cells_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cycloneive/cells_sim.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cyclonev/cells_arith.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cyclonev/cells_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/cyclonev/cells_sim.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/max10/cells_arith.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/max10/cells_map.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/max10/cells_sim.v	[changed mode: 0755->0644]	diff \| blob \| history
techlibs/intel/synth_intel.cc	[changed mode: 0755->0644]	diff \| blob \| history

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