Fix RAM64M model to have 6 bit address bus
authorEddie Hung <eddie@fpgeh.com>
Fri, 13 Dec 2019 02:52:03 +0000 (18:52 -0800)
committerEddie Hung <eddie@fpgeh.com>
Fri, 13 Dec 2019 02:52:03 +0000 (18:52 -0800)
commit50e0c835606a94c825079a63fc026c906c9985e0
tree4347fee988aa882b1b640df4fbd1abbf585c2bbf
parent037d1a03df20b9c445790728bb80e1818d1edafa
Fix RAM64M model to have 6 bit address bus
techlibs/xilinx/cells_sim.v