New specification for width and signedness
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 29 Nov 2012 20:22:38 +0000 (21:22 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 29 Nov 2012 20:22:38 +0000 (21:22 +0100)
commit50ed73c937b073efc9452cdcf09e29d2d87f089a
tree77e7b50093471961a0acbeb60f31a10ad93480d1
parent6eebfce44aa62ca0e2010e2250fa96017d4b4382
New specification for width and signedness
40 files changed:
examples/basic/arrays.py
examples/basic/lm32_inst.py
examples/basic/namer.py
examples/basic/simple_gpio.py
examples/basic/using_record.py
examples/dataflow/arithmetic.py [deleted file]
examples/dataflow/dma.py
examples/dataflow/fibonacci.py [deleted file]
examples/dataflow/misc.py
examples/dataflow/structuring.py
examples/pytholite/basic.py
examples/pytholite/uio.py
examples/sim/basic1.py
examples/sim/basic2.py
examples/sim/dataflow.py
examples/sim/fir.py
migen/actorlib/ala.py [deleted file]
migen/actorlib/dma_asmi.py
migen/actorlib/dma_wishbone.py
migen/actorlib/misc.py
migen/actorlib/structuring.py
migen/bank/description.py
migen/bus/asmibus.py
migen/bus/simple.py
migen/bus/wishbone.py
migen/bus/wishbone2asmi.py
migen/corelogic/buffers.py
migen/corelogic/divider.py
migen/corelogic/fsm.py
migen/corelogic/misc.py
migen/corelogic/record.py
migen/corelogic/roundrobin.py
migen/fhdl/structure.py
migen/fhdl/tools.py
migen/fhdl/verilog.py
migen/flow/actor.py
migen/flow/isd.py
migen/flow/plumbing.py
migen/pytholite/reg.py
migen/sim/generic.py