radeon/llvm: Add special nodes for SALU operations on VCC
authorTom Stellard <thomas.stellard@amd.com>
Wed, 25 Jul 2012 12:30:32 +0000 (08:30 -0400)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 27 Jul 2012 17:08:08 +0000 (17:08 +0000)
commit50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48
treeacc1b4b0a305aff1f771399445614bf10302fd24
parentc424975572af2edd46863e5bb9fe3c51c96b4f9b
radeon/llvm: Add special nodes for SALU operations on VCC

The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit.  In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
src/gallium/drivers/radeon/AMDGPUISelLowering.h
src/gallium/drivers/radeon/SIISelLowering.cpp
src/gallium/drivers/radeon/SIISelLowering.h
src/gallium/drivers/radeon/SIInstrFormats.td
src/gallium/drivers/radeon/SIInstrInfo.td
src/gallium/drivers/radeon/SIInstructions.td