[AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
authorRichard Sandiford <richard.sandiford@arm.com>
Mon, 30 Sep 2019 15:23:30 +0000 (15:23 +0000)
committerRichard Sandiford <rsandifo@gcc.gnu.org>
Mon, 30 Sep 2019 15:23:30 +0000 (15:23 +0000)
commit51051f474a768d285714d713f1b7535d6a139350
tree2d51c313466b59810bdc099b5211c548a806233f
parent4baad9863a5df7ec01b42afecd4170f4d58a1aac
[AArch64] Strengthen aarch64_hard_regno_call_part_clobbered

The aarch64_vector_pcs handling in aarch64_hard_regno_call_part_clobbered
checks whether the mode might be bigger than 16 bytes, since on SVE
targets the (non-SVE) vector PCS only guarantees that the low 16 bytes
are preserved.  But for multi-register modes, we should instead test
whether each single-register part might be bigger than 16 bytes.
(The size is always divided evenly between registers.)

The testcase uses XImode as an example where this helps.

2019-09-30  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_hard_regno_call_part_clobbered):
For multi-registers modes, test how big each register part is.

gcc/testsuite/
* gcc.target/aarch64/torture/simd-abi-8.c: New test.

From-SVN: r276305
gcc/ChangeLog
gcc/config/aarch64/aarch64.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/torture/simd-abi-8.c [new file with mode: 0644]