RISC-V: Promode modes of constant loads for store insns.

RISC-V: Promode modes of constant loads for store insns.

This improves optimization of code storing constants to memory.  Given this
testcase:
    void sub1 (int *a, long long *b) { *a = 1; *b = 1; }
an unpatched rv64 compiler emits two li instructions, one for an SImode pseudo
and one for a DImode pseudo.  With the patch, we get a single DImode li insn.

	gcc/
	* config/riscv/riscv-protos.h (riscv_move_integer): Add machine_mode
	parameter.
	* config/riscv/riscv.c (riscv_move_integer): New parameter orig_mode.
	Pass orig_mode to riscv_build_integer.
	(riscv_split_integer): Pass mode to riscv_move_integer.
	(riscv_legitimize_const_move): Likewise.
	(riscv_legitimize_move): For MEM dest and CONST_INT src case, new local
	promoted_mode.  Replace force_reg call with code to load constant into
	promoted reg and then subreg it for the store.
	* config/riscv/riscv.md (low<mode>+1): Pass <GPR:MODE>mode to
	riscv_move_integer.

	gcc/testsuite/
	* gcc.target/riscv/load-immediate.c: New.

From-SVN: r270621