i965/fs: Use the actual hardware g0 register for texel offset setup.
authorKenneth Graunke <kenneth@whitecape.org>
Thu, 27 Oct 2011 05:41:07 +0000 (22:41 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Fri, 28 Oct 2011 19:11:52 +0000 (12:11 -0700)
commit512431b3575eb5f2c27d8795c5e2191047ebb5ed
tree3e61cb9b6690a208d28c8dc2d46b3aa8dffd1b5c
parent058e712415a8160479f0df13367b1171ffd66902
i965/fs: Use the actual hardware g0 register for texel offset setup.

The idea here is to set up the message header with the Sampler State
pointer which the hardware provides as part of the PS Thread Payload in
register g0.

Unfortunately, the existing code

   fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD))

actually references "virtual GRF 0" rather than the hardware g0.  This
is just some arbitrary GRF temporary which will get register allocated.

So, we ended up setting up the header with garbage.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp