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(parent: 55fc9d2) | patch
Preliminary AXI4Lite CSR bridge support
authorSergiusz Bazanski <q3k@q3k.org>
Tue, 20 Feb 2018 21:27:51 +0000 (21:27 +0000)
committerSergiusz Bazanski <q3k@q3k.org>
Tue, 20 Feb 2018 21:27:51 +0000 (21:27 +0000)
commit512ed2b3d60694998a4d905a9d7c130e257e9981
tree65893d481bc99e9bf7d54f4775ed5005846e2459tree
parent55fc9d2d6bdc343f569ded3ab3415f260f2a96abcommit | diff
Preliminary AXI4Lite CSR bridge support

This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
litex/soc/interconnect/axi.py [new file with mode: 0644] blob