bug #672: invert testing in sv.minmax and add Rc=1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Dec 2023 15:38:26 +0000 (15:38 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 9 Dec 2023 06:46:35 +0000 (06:46 +0000)
commit517f79ed486f44c8cc79485e6cc39a3ff553b947
tree56b592607599bbc3e80a270cefd2a15579af9a36
parentb077590a8f3fbe12c9dd2679d0709804bc43e5ac
bug #672: invert testing in sv.minmax and add Rc=1
src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py