sim,cpu,mem,arch: Introduced MasterInfo data structure
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 4 Apr 2018 15:27:04 +0000 (16:27 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 27 Apr 2018 16:00:28 +0000 (16:00 +0000)
commit5187a24d496cd16bfe440f52ff0c45ab0e185306
treec491ebdad23a5f9e57ef62ffeabcf2b87289f5ce
parent685cf2d1f8ae2f2ca3168a650efa1d36120783fe
sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
19 files changed:
src/arch/arm/stage2_mmu.cc
src/arch/x86/pagetable_walker.hh
src/cpu/base.cc
src/cpu/checker/cpu.cc
src/cpu/testers/directedtest/DirectedGenerator.cc
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/rubytest/RubyTester.cc
src/cpu/testers/traffic_gen/traffic_gen.cc
src/cpu/trace/trace_cpu.cc
src/dev/dma_device.cc
src/gpu-compute/compute_unit.cc
src/gpu-compute/dispatcher.cc
src/mem/cache/prefetch/base.cc
src/mem/external_master.cc
src/mem/mem_master.hh [new file with mode: 0644]
src/mem/ruby/slicc_interface/AbstractController.cc
src/sim/system.cc
src/sim/system.hh