read_verilog cells_box.v before techmap
authorEddie Hung <eddie@fpgeh.com>
Tue, 16 Apr 2019 19:41:56 +0000 (12:41 -0700)
committerEddie Hung <eddie@fpgeh.com>
Tue, 16 Apr 2019 19:41:56 +0000 (12:41 -0700)
commit51896953626ddf7cffdbddfe64e8d85264d968a8
tree0f819f0560bd710ad708a861da908deafc8e1945
parentd259e6dc14dadf9101116c622569f5b961adde69
read_verilog cells_box.v before techmap
techlibs/xilinx/synth_xilinx.cc