base, sim: Make ByteOrder into a ScopedEnum accessible to Python
authorAndreas Sandberg <andreas.sandberg@arm.com>
Fri, 21 Aug 2020 10:53:18 +0000 (11:53 +0100)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Tue, 8 Sep 2020 16:24:00 +0000 (16:24 +0000)
commit51992fa80af477097ece177610ec9e05aef03df4
tree5e18a52aec3f00a14ec2ffc975d4fc66a83f5b51
parent2ea459e6cdae27e2d071593becf98ef86556fc92
base, sim: Make ByteOrder into a ScopedEnum accessible to Python

There is currently no good way of passing a byte order as a Param
since the ByteOrder type is defined in C++. Make this into a generated
ScopedEnum that can be used in Params.

Change-Id: I990f402340c17c4e0799de57df19516ae61794d4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
43 files changed:
src/arch/arm/aapcs32.hh
src/arch/arm/freebsd/freebsd.hh
src/arch/arm/isa_traits.hh
src/arch/arm/linux/linux.hh
src/arch/arm/process.cc
src/arch/arm/utility.hh
src/arch/generic/memhelpers.hh
src/arch/mips/isa_traits.hh
src/arch/mips/linux/linux.hh
src/arch/mips/process.cc
src/arch/power/isa_traits.hh
src/arch/power/linux/linux.hh
src/arch/power/process.cc
src/arch/riscv/isa_traits.hh
src/arch/riscv/linux/linux.hh
src/arch/sparc/isa_traits.hh
src/arch/sparc/linux/linux.hh
src/arch/sparc/process.cc
src/arch/sparc/solaris/solaris.hh
src/arch/x86/isa_traits.hh
src/arch/x86/linux/linux.hh
src/arch/x86/process.cc
src/base/pixel.cc
src/base/pixel.hh
src/base/types.hh
src/base/vnc/vncserver.cc
src/dev/arm/amba_device.cc
src/dev/arm/fvp_base_pwr_ctrl.cc
src/dev/arm/generic_timer.cc
src/dev/arm/gic_v3.cc
src/dev/arm/gic_v3_its.cc
src/dev/arm/hdlcd.cc
src/dev/arm/kmi.cc
src/dev/arm/pl011.cc
src/dev/arm/pl111.cc
src/dev/arm/rtc_pl031.cc
src/dev/arm/watchdog_sp805.cc
src/dev/serial/simple.cc
src/mem/cache/prefetch/base.hh
src/mem/packet_access.hh
src/python/m5/params.py
src/sim/byteswap.hh
src/sim/byteswap.test.cc