fhdl/verilog: remove empty cases
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 18 Nov 2012 15:32:51 +0000 (16:32 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 18 Nov 2012 15:32:51 +0000 (16:32 +0100)
commit51e2e6ecd076178584910f231dbace7656eb23cd
treebca0126a58841218d038f1c3aecf66b9af55f2a2
parent89643bc4346d2f31a3dfb1c7852768ec4a4b550a
fhdl/verilog: remove empty cases
migen/fhdl/verilog.py