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(parent: 637c18c) | patch
back.rtlil: lower maximum accepted wire size.
authorwhitequark <whitequark@whitequark.org>
Wed, 22 Jul 2020 14:43:44 +0000 (14:43 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 14:54:35 +0000 (14:54 +0000)
commit520f6dd02b042fce4a2f0bf9881bf90b066a12cf
tree172663677ad25bdf57ac59867d72a45920d86d7ctree
parent637c18ca2b3aa60588c4f594276cfc86b0ddcbb0commit | diff
back.rtlil: lower maximum accepted wire size.

In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.
nmigen/back/rtlil.py diff | blob | history