Add arrival times for SRL outputs
authorEddie Hung <eddie@fpgeh.com>
Mon, 19 Aug 2019 22:15:43 +0000 (15:15 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 19 Aug 2019 22:15:43 +0000 (15:15 -0700)
commit526e0813427aae24b9df2eacbbb8c067bdfd5eec
tree73a0ab6fd54626150011ce043a02f1a20de984bf
parent45d4b33f0c2140d764a3a16b14286f6651fbbae6
Add arrival times for SRL outputs
techlibs/xilinx/cells_sim.v