sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
authorXiaoyu Ma <xiaoyuma@google.com>
Thu, 30 Nov 2017 15:48:52 +0000 (07:48 -0800)
committerGabe Black <gabeblack@google.com>
Fri, 12 Jan 2018 00:57:56 +0000 (00:57 +0000)
commit5320a97ced43d4452014ff54c0ba45246db90a00
tree8048a3c9f79b83deb64b7c5454bd560b2b115208
parentcc51037e8074949bc9e7638babfb597490d007ec
sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.

Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
src/cpu/BaseCPU.py