vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
authorwhitequark <whitequark@whitequark.org>
Thu, 21 May 2020 08:57:30 +0000 (08:57 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 13:32:10 +0000 (13:32 +0000)
commit535b007f28af7cb46fe371c25af636459599bdf3
tree76b43577ae2407c484bb5240194f119603a5f89a
parent06c4baf44efaa96095dda125d45060f8004827ca
vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.

In commit 892cff05, `-decimal` was used when writing Verilog for
Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *)
differently in violation of Verilog LRM. However, it is possible
to avoid that workaround by using (* keep="TRUE" *). Do that,
and remove `-decimal` to avoid special-casing 32-bit constants.

Refs #373.
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_ultrascale.py