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(parent: 11c8a9e) | patch
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into...
authorUdi Finkelstein <github@udifink.com>
Wed, 24 Oct 2018 23:37:56 +0000 (02:37 +0300)
committerUdi Finkelstein <github@udifink.com>
Wed, 24 Oct 2018 23:37:56 +0000 (02:37 +0300)
commit536ae16c3abcf3fef1dd14df8733bf51fa1bce1a
tree00838e80593c2d0a8d46c1b448a44ddd62a4c796tree
parent11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67dcommit | diff
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
14 files changed:
frontends/verilog/verilog_parser.y diff | blob | history
tests/errors/syntax_err01.v [new file with mode: 0644] blob
tests/errors/syntax_err02.v [new file with mode: 0644] blob
tests/errors/syntax_err03.v [new file with mode: 0644] blob
tests/errors/syntax_err04.v [new file with mode: 0644] blob
tests/errors/syntax_err05.v [new file with mode: 0644] blob
tests/errors/syntax_err06.v [new file with mode: 0644] blob
tests/errors/syntax_err07.v [new file with mode: 0644] blob
tests/errors/syntax_err08.v [new file with mode: 0644] blob
tests/errors/syntax_err09.v [new file with mode: 0644] blob
tests/errors/syntax_err10.v [new file with mode: 0644] blob
tests/errors/syntax_err11.v [new file with mode: 0644] blob
tests/errors/syntax_err12.v [new file with mode: 0644] blob
tests/errors/syntax_err13.v [new file with mode: 0644] blob