git.libre-soc.org Git - gem5.git/commit

author	Gabe Black <gblack@eecs.umich.edu>
	Mon, 27 Aug 2007 03:24:18 +0000 (20:24 -0700)
committer	Gabe Black <gblack@eecs.umich.edu>
	Mon, 27 Aug 2007 03:24:18 +0000 (20:24 -0700)
commit	537239b278f7b8171d2eb09ef7f99c332266c48f
tree	31984b63cc542f0a57ca96262477575ab0130c09	tree
parent	f738afb865cd82487d6300259d6e87fb50660d2a	commit \| diff

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1

58 files changed:

src/arch/alpha/SConscript		diff \| blob \| history
src/arch/alpha/ev5.cc		diff \| blob \| history
src/arch/alpha/faults.cc		diff \| blob \| history
src/arch/alpha/faults.hh		diff \| blob \| history
src/arch/alpha/isa_traits.hh		diff \| blob \| history
src/arch/alpha/miscregfile.cc		diff \| blob \| history
src/arch/alpha/miscregfile.hh		diff \| blob \| history
src/arch/alpha/process.cc		diff \| blob \| history
src/arch/alpha/regfile.cc		diff \| blob \| history
src/arch/alpha/utility.hh		diff \| blob \| history
src/arch/mips/MipsTLB.py	[new file with mode: 0644]	blob
src/arch/mips/SConscript		diff \| blob \| history
src/arch/mips/tlb.cc	[new file with mode: 0644]	blob
src/arch/mips/tlb.hh	[new file with mode: 0644]	blob
src/arch/sparc/SConscript		diff \| blob \| history
src/arch/sparc/faults.cc		diff \| blob \| history
src/arch/sparc/faults.hh		diff \| blob \| history
src/arch/sparc/isa_traits.hh		diff \| blob \| history
src/arch/sparc/process.cc		diff \| blob \| history
src/arch/sparc/tlb.cc		diff \| blob \| history
src/arch/sparc/tlb.hh		diff \| blob \| history
src/arch/x86/SConscript		diff \| blob \| history
src/arch/x86/X86TLB.py	[new file with mode: 0644]	blob
src/arch/x86/tlb.cc	[new file with mode: 0644]	blob
src/arch/x86/tlb.hh		diff \| blob \| history
src/cpu/BaseCPU.py		diff \| blob \| history
src/cpu/checker/thread_context.hh		diff \| blob \| history
src/cpu/o3/O3CPU.py		diff \| blob \| history
src/cpu/o3/alpha/cpu_builder.cc		diff \| blob \| history
src/cpu/o3/alpha/params.hh		diff \| blob \| history
src/cpu/o3/checker_builder.cc		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/cpu.hh		diff \| blob \| history
src/cpu/o3/fetch_impl.hh		diff \| blob \| history
src/cpu/o3/mips/params.hh		diff \| blob \| history
src/cpu/o3/sparc/cpu_builder.cc		diff \| blob \| history
src/cpu/o3/sparc/params.hh		diff \| blob \| history
src/cpu/o3/thread_context.hh		diff \| blob \| history
src/cpu/ozone/checker_builder.cc		diff \| blob \| history
src/cpu/ozone/cpu.hh		diff \| blob \| history
src/cpu/ozone/cpu_builder.cc		diff \| blob \| history
src/cpu/ozone/cpu_impl.hh		diff \| blob \| history
src/cpu/ozone/simple_cpu_builder.cc		diff \| blob \| history
src/cpu/ozone/simple_params.hh		diff \| blob \| history
src/cpu/simple/atomic.cc		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history
src/cpu/simple/base.hh		diff \| blob \| history
src/cpu/simple/timing.cc		diff \| blob \| history
src/cpu/simple_thread.cc		diff \| blob \| history
src/cpu/simple_thread.hh		diff \| blob \| history
src/cpu/thread_context.hh		diff \| blob \| history
src/sim/SConscript		diff \| blob \| history
src/sim/process.cc		diff \| blob \| history
src/sim/process.hh		diff \| blob \| history
src/sim/system.cc		diff \| blob \| history
src/sim/system.hh		diff \| blob \| history
src/sim/tlb.cc	[new file with mode: 0644]	blob
src/sim/tlb.hh	[new file with mode: 0644]	blob

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