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(parent: 63c19ff) | patch
wire up missing register bits.
authorbunnie <bunnie@kosagi.com>
Sat, 18 Jul 2020 19:00:25 +0000 (03:00 +0800)
committerbunnie <bunnie@kosagi.com>
Sat, 18 Jul 2020 19:00:25 +0000 (03:00 +0800)
commit53a567daef000f2d2457375bf610239c442fbec1
treee05bc3ecc2b2d0c063088f8da66929b7f71266f9tree
parent63c19ff45fa3421d2affd1b987d6a92112a78710commit | diff
wire up missing register bits.

Not sure how they went missing...but just noticed them.
litex/soc/cores/i2s.py diff | blob | history