mem-ruby: Replace SLICC queueMemory calls with enqueue
authorMatt Poremba <matthew.poremba@amd.com>
Thu, 8 Feb 2018 19:48:21 +0000 (11:48 -0800)
committerMatthew Poremba <matthew.poremba@amd.com>
Wed, 8 Apr 2020 23:40:57 +0000 (23:40 +0000)
commit53b6e21c631a0bb227aae0b474884022ed191f59
treec2e542b3e1131d306467115469b2035c58550b29
parent8b2b0f8d7154e7d70542879bd66097b37a871a84
mem-ruby: Replace SLICC queueMemory calls with enqueue

Calls to queueMemoryRead and queueMemoryWrite do not consider the size
of the queue between ruby directories and DRAMCtrl which causes infinite
buffering in the queued port between the two. This adds a MessageBuffer
in between which uses enqueues in SLICC and is therefore size checked
before any SLICC transaction pushing to the buffer can occur, removing
the infinite buffering between the two.

Change-Id: Iedb9070844e4f6c8532a9c914d126105ec98d0bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27427
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
25 files changed:
configs/learning_gem5/part3/msi_caches.py
configs/learning_gem5/part3/ruby_caches_MI_example.py
configs/ruby/GPU_RfO.py
configs/ruby/GPU_VIPER.py
configs/ruby/GPU_VIPER_Baseline.py
configs/ruby/GPU_VIPER_Region.py
configs/ruby/MESI_Two_Level.py
configs/ruby/MI_example.py
configs/ruby/MOESI_CMP_directory.py
configs/ruby/MOESI_CMP_token.py
configs/ruby/MOESI_hammer.py
src/learning_gem5/part3/MSI-dir.sm
src/mem/ruby/protocol/MESI_Two_Level-dir.sm
src/mem/ruby/protocol/MI_example-dir.sm
src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
src/mem/ruby/protocol/MOESI_hammer-dir.sm
src/mem/ruby/protocol/RubySlicc_Defines.sm
src/mem/ruby/protocol/RubySlicc_MemControl.sm
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/slicc/symbols/StateMachine.py